Publications

Masson P. , Autran J.L., Raynaud C., Flament O., Paillet P., Surface potential determination in irradiated MOS transistors combining current-voltage and charge pumping measurements. IEEE Transactions on Nuclear Science , 1998, Vol. 45, No. 3, p. 1355-1364.

Masson P. , Ghibaudo G., Autran J.L., Morfouli P., Brini J., Influence of the quadratic mobility degradation factor on the low frequency noise in MOS transistors. IEE Electronics Letters, 1998, Vol. 34, No. 20, p. 1977-1978.

Masson P. , Autran J.L., Brini J., On the tunneling component of charge pumping current in Ultra-thin gate oxide MOSFET's. IEEE Electron Device Letters, 1999, Vol. 20, No. 2, p. 92-94

Masson P. , Morfouli P., Autran J.L., Brini J., Balland B., Vogel E.M., Wortman J.J., Electrical properties of oxynitride films using noise and charge pumping measurements. Journal of Non-Crystalline Solids, 1999, Vol. 245, No. 1-3 p. 54-58

Masson P. , Morfouli P., Autran J.L., Wortman J.J., Electrical characterization of n-channel MOSFET's with oxynitride gate dielectric formed by Low-Pressure Rapid Thermal Chemical Vapor Deposition. Microelectronic Engineering, 1999, Vol 48, No. 1-4, p. 211-214

Autran J.L., Masson P., Freud N., Raynaud C., Riekel C., Micro-Irradiation experiments in MOS transistors using synchrotron radiation. IEEE Transactions on Nuclear Science, 2000, Vol. 47, No. 3, p. 574-579

Masson P. , Autran J.L., Ghibaudo G., An improved time domain analysis of the charge pumping current. Journal of Non-Crystalline Solids, 2001, Vol. 280 No. 1-3, p. 255-260

De Salvo B., Ghibaudo G., Pananakakis G., Masson P., Baron T., Buffet N., Fernandes A , Guillaumot B., Experimental and theoretical investigation of nano-crystal and nitride-trap memory devices, IEEE Transactions on Electron Devices, Vol. 48, No. 8, 2001, p. 1789-1799

Weintraub C.E., Vogel E., Hauser J.R., Yang N., Misra V., Wortman J.J., Ganem J. and Masson P., Study of low-frequency charge pumping on thin stacked dielectrics, IEEE Transactions on Electron Devices, Vol. 48, No. 12, 2001, p. 2754-2762

P. Masson , J.L. Autran, D. Munteanu, DYNAMOS: a numerical MOSFET model including quantum-mechanical and near-interface trap transient effects, Solid-State Electronics , Vol. 46, 2002, p 1051-1059

L. Militaru, P. Masson, G. Geguan, Three level charge pumping on a single interface trap, IEEE Electron Device Letters, Vol. 23, No. 2, 2002, p. 94-96

P. Masson , J.L. Autran, M. Houssa, X. Garros and C. Leroux, Frequency characterization and modeling of interface traps in metal-oxide-semiconductor structures with HfO 2 gate dielectrics from a capacitance point-of-view, Applied Physic Letters, Vol. 81, No. 18, 2002, p. 3392-3394

R. Laffont, P. Masson, S. Bernardini, R. Bouchakour, J.M. Mirabel, A new floating compact model applied to Flash memory cell, Journal of Non-Crystalline Solids , Vol. 322, Issues 1-3, 2003, p. 250-255

S. Bernardini, P. Masson, M. Houssa, Effect of fixed dielectric charges on tunneling transparency in MIM and MIS structures, Microelectronic Engineering, Vol. 72, 2004, p. 90-95

L. Lopez, P. Masson, D. Née, R. Bouchakour, Temperature and drain voltage dependence of Gate Induce Drain Leakage, Microelectronic Engineering, Vol. 72, 2004, p. 101-105

A. Villaret, R. Ranica, P. Masson, P. Malinge, P. Mazoyer, P. Candelier, F. Jacquet, S. Cristoloveanu, T. Skotnicki, Mechanisms of charge modulation in floating body of triple-well N-MOSFET capacitor-less DRAMs, Microelectronic Engineering, Vol. 72, 2004, p. 434-439

S. Bernardini, P. Masson, M. Houssa, F. Lalande, Origin and repartition of the oxide fixed charges generated by electrical stress in memory tunnel oxide, Applied Physic Letters, Vol. 84, No. 21, 2004, p. 4251-4253

A. Villaret, R. Ranica, P. Malinge, P. Masson, P. Mazoyer, P. Candelier, T. Skotnicki, Further Insight on the Modelling and Characterization of Triple-Well Capacitorless DRAMs, IEEE Transactions on Electron Devices , Vol. 52, No. 11, 2005, p. 2447-2454

R. Ranica, A. Villaret , P. Mazoyer, S. Monfray, D.Chanemougame, P. Masson, C. Dray, P. Waltz, R. Bez, R. Bouchakour, T. Skotnicki, A new 40nm SONos structure based on backside trapping for nanoscale memories, IEEE Transactions on Nanotechnology , Vol. 4, No. 5, 2005, p. 581-587

Perniola L., Bernardini S., Iannaccone G., Masson P., DeSalvo B., Ghibaudo G., Gerardi C., Analytical Model of the Effects of a Nonuniform Distribution of Stored Charge on the Electrical Characteristics of Discrete-Trap Nonvolatile Memories, IEEE Transactions on Nanotechnology, Vol. 4, No. 3, May 2005, p. 360-368

Gilibert F., Rideau D., Dray A., Agut F., Minondo M., Juge A., Masson P., Bouchakour R., Characterization and modeling of gate-induced-drain-leakage, IEICE Transactions on Electronics, E88C (5), 2005, p. 829-837

Ranica R., Villaret A., Malinge P., Candelier P., Masson P., Bouchakour R., Mazoyer P., Skotnicki T., Modelling of the 1T-bulk capacitor-less DRAM cell with improved performances: the way to scaling, Solid-State Electronics, Vol. 49, No. 11, 2005, p. 1759-1766

Sophie Puget, Germain Bossu, Pascal Masson, Pascale Mazoyer, Rossella Ranica, Alexandre Villaret, Philippe Lorenzini, Jean-Michel Portal, Denis Rideau, Gérard Ghibaudo, Rachid Bouchakour, Gilles Jacquemod, Thomas Skotnicki, Modelling the Independent Double Gate Transistor in Accumulation Regime for 1T DRAM Application, IEEE Transaction On Electron Devices, Vol. 57, No. 4, 2010, à paraître en avril

Pascale Mazoyer, Sophie Puget, Germain Bossu, Pascal Masson, Philippe Lorenzini and Jean Michel Portal, Thin film embedded memory solutions, Current Applied Physics, Vol.10, Issue 1, supplement 1, 2010, p. e9 – e12

R. Llido, P. Masson, A. Regnier, V. Goubier, G. Haller, V. Pouget, D. Lewis, Effects of 1064 nm laser on MOS capacitor, Microelectonics Reliability, Vol. 52, 2012, p. 1816-1821

P. Chiquet, P. Masson, R. Laffont, G. Micolau, J. Postel-Pellerin, F. Lalande, B. Bouteille, J-L. Ogier, Investigation of the effects of constant voltage stress on thin SiO 2 layers using dynamic measurement protocols, Microelectonics Reliability, Vol. 52, 2012, p.1895-1900

Y. Joly, L. Lopez, J.-M. Portal, H. Aziza, P. Masson,J.-L. Ogier, Y. Bert, F. Julien and P. Fornara, , Threshold voltage asymmetric degradationon octagonal MOSFET during HCI stress, IEE Electronics Letters , 2012, Vol. 48, No. 14, p. 879-881

G. Just, V. Della Marca, A. Régnier, J-L. Ogier, J. Postel-Pellerin, F. Lalande, J-M Portal and P. Masson, Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability, Journal of Low Power Electronics (JOLPE), 2012, Vol. 8, p. 717-724

Y. Joly, L. Lopez, L. Truphemus, JM. Portal, H. Aziza, F. Julien, P. Fornara, P. Masson, JL. Ogier, Y. Bert, Gate Voltage Matching Investigation for Low Power Analog Applications, IEEE Transactions on Electron Devices, 2013, Vol. 60, No 3, p.1263-1267

Q. Hubert, M. Carmona, B. Rebuffat, J. Innocenti, P. Masson, L. Masoero, F. Julien, L. Lopez, P. Chiquet, All regimes mobility extraction using split C–V technique enhanced with charge-sheet model, Solid-State Electronics, Vol. 111, 2015, p. 52–57

P. Devoge, H. Aziza, P. Lorenzini, P. Masson, F. Julien, A. Marzaki, A. Malherbe, J. Delalleau, T. Cabout, A. Regnier, S. Niel, Hot-carrier reliability and performance study of a variable gate-to-drain/source overlap transistor, Microelectronic Reliability, 2022

P. Masson , J.L. Autran, C. Raynaud, O. Flament, P. Paillet, Surface potential determination in irradiated MOS transistors combining current-voltage and charge pumping measurements. Proceeding of the 4 th IEEE European Conference on radiation and its Effects on Components and Systems (RADECS), Cannes 1997, Proceeding RADECS 97TH8294, p. 26-35

P. Masson , P. Morfouli, J.L. Autran, J. Brini, B. Balland, E.M. Vogel, J.J. Wortman, Electrical characterization of thin RTO and RTCVD silicon oxynitride films using noise and charge pumping measurements. 2 nd French-Italian Symposium on SiO 2 and advanced dielectrics, L’Aquila (Italie), juin 1998

P. Masson , P. Morfouli, J.L. Autran, et J.J. Wortman, Electrical characterization of n-channel MOSFET's with oxynitride gate dielectric formed by Low-Pressure Rapid Thermal Chemical Vapor Deposition. INFOS , Erlangen (Allemagne) 16-19 juin 1999

J.L. Autran, P. Masson, N. Freud, C. Raynaud, C. Riekel, Micro-Irradiation experiments in MOS transistors using synchrotron radiation Proceeding of the 5 th IEEE European Conference on radiation and its Effects on Components and Systems (RADECS), Fontevraud (France) 1999, Proceeding RADECS 99TH8471, p. 256-261

B. De Salvo, R. Clerc, P. Masson, Y.A. Ahouassa, G. Ghibaudo, Electrical characterization and modelling of ultra-thin (1.8-3.4 nm) gate oxides, ProceedingsESSDERC, Leuven (Belgique) 1999, p. 168-171

J.L. Autran, P. Masson, G. Ghibaudo, Challenges in interface trap characterization of deep sub-micron MOS devices using charge pumping techniques (invited), MRS Boston 1999, Mat. Res. Soc. Symp. Proc. Vol. 592, p. 275-288

Raynaud C., J.L. Autran, P. Masson, M. Bidaud, A. Poncet, Analysis of MOS device capacitance-voltage characteristics based on the self-consistent solution of the schrödinger and Poisson equations., MRS Boston 1999, Mat. Res. Soc. Symp. Proc. Vol. 592, p. 159-164

P. Masson , J.L. Autran, G. Ghibaudo, An improved time domain analysis of the charge pumping current. 3 nd French-Italian Symposium on SiO 2 and advanced dielectrics, Fuveau (France), juin 2000

J.L. Autran, M. Bidaud, N. Emonet, P. Masson, A. Poncet, Quantum mechanical modeling of gate tunneling currents in metal-oxide-semiconductor devices. 3 nd French-Italian Symposium on SiO 2 and advanced dielectrics, Fuveau (France), juin 2000

P. Masson , J.L. Autran, D. Munteanu, DYNAMOS: a numerical MOSFET model including quantum-mechanical and near-interface trap transient effects, 2 nd European Workshop on Ultimate Integration of Silicon (ULIS), Grenoble, février 2001

B. De Salvo, G. Ghibaudo, G. Pananakakis, P. Masson, A. Fernandes, T. Baron, N. Buffet, D. Mariolle, B. Guillaumot, Electrical characterisation and modeling of memory-cell structures employing discrete-trap type storage nodes, Silicon Nanoelectronics Workshop, Kyoto (Japon), juin 2001

L. Militaru, P. Masson, V. Celibert, C Leroux, Single Trap Characterization in 50nm MOS Transistors by Charge Pumping Measurements, ESSDERC, Nuremberg (Allemagne), septembre 2001

A. Fernandez, B. DeSalvo, P. Masson, G. Pananakakis, G. Ghibaudo, T. Baron, N. Buffet, D Mariolle, G. Ghibaudo, Electrical characterization of memory-cell structure employing ultra-thin Al 2O 3 film as storage node, ESSDERC 2001, Nuremberg (Allemagne), septembre 2001

A. Fernandez, B. DeSalvo, T. Baron, J.F. Damlencourt, A.M. Papon, D. Lafond, D. Mariolle, B. Guillaumot, P. Besson, P. Masson, G. Ghibaudo, G. Pananakakis, F. Martin, S. Haukka, Memory characteristics of Si quantum dot devices with SiO 2/Al 2O 3 tunneling dielectrics, IEDM 2001 , Washington (USA), decembre 2001

P. Masson , J.L. Autran, X. Garros and C. Leroux, Frequency characterization and modeling of interface traps in metal-oxide-semiconductor capacitors with polysilicon gate and HfO 2 high- k dielectrics, 3 rd European Workshop on Ultimate Integration of Silicon (ULIS), Munich (Allemagne), June 2002

P. Masson , L. Militaru, B. DeSalvo, G. Ghibaudo, V. Celibert, T. Baron, Nano-crystal memory devices characterization using the charge pumping technique, in "Proceedings of ESSDERC'2002, 32 nd European Solid-State Devices Research Conference", University of Bologna, G. Baccarani, Firenze (Italy), p. 235-238, 2002

R. Laffont, P. Masson, R. Bouchakour, S. Bernardini, J.M. Mirabel, A new Flash physical model based on Pao and Sah approach, 4 nd French-Italian Symposium on SiO 2 and advanced dielectrics, Florence (Italy), septembre 2002

B. Guillaumot, X. Garros, F. Lime, K. Oshima, B. Tavel, J.A. Chroboczek, P. Masson, R. Truche, A.M. Papon, F. Martin, J.F. Damlencourt, S. Maitrejean, M. Rivoire, C. Leroux, S. Cristoloveanu, G. Ghibaudo, J.L. Autran, T. Skotnicki, S. Deleonibus, 75 nm damascene metal gate and high-k integration for advanced CMOS devices, IEDM 2002, San Francisco (USA), decembre 2002

A. Villaret, R. Ranica, P. Masson, P. Mazoyer, S. Cristoloveanu, T. Skotnicki; Mechanisms of charge modulation in floating body of triple-well N-MOSFET capacitor-less DRAMs, ProceedingINFOS’2003, Barcelona (Espagne), 2003, p. WS3-7

R. Laffont, P. Masson, P. Canet, B. Delsuc, R. Bouchakour, J.M. Mirabel, Fowler Nordheim current determination during EEPROM cell operation, ESSDERC’2003, Estoril (Portugal), ISBN 0-7803-7999-3, 2003, p. 71-74

B. Guillaumot, X. Garros, F. Lime, K. Oshima, J.A. Chrobovzek, P. Masson, R. Truche, A.M. Papon, F. Martin, J.F Damlencourt, S. Maitrejean, M. Rivoire, C. Leroux, S. Cristoloveanu, G. Ghibaudo, T. Skotnicki, S. Deleonibus, Metal gate high- k integration for advanced CMOS devices, 8 th International Symposium on Plasma and Process Induced Damage (P2ID), 24-25 April, 2003, p. 56-60

S. Bernardini, R. Laffont, P. Masson, G. Ghibaudo, S. Lombardo, B. De Salvo, C. Gerardi, A predictive nano-crystal Flash memory simulator, in "Proceedings of 4 rd European Workshop on Ultimate Integration of Silicon (ULIS) ", Udine (Italy), June 2003, p. 143-146

S. Bernardini, P. Masson, M. Houssa, Effect of fixed dielectric charges on tunneling transparency in MIM and MIS structures, INFOS’2003, Barcelone (Spain), 2003, p. PS12

L. Lopez, P. Masson, D. Née, R. Bouchakour, Temperature and drain voltage dependence of Gate Induce Drain Leakage, INFOS’2003, Barcelone (Spain), 2003, p. PS14

S. Bernardini, P. Masson, M. Houssa, F. Lalande, Impact of oxide charge trapping on I-V characteristics of MIM capacitor, ESSDERC’2003, Estoril (Portugal), 2003, p. 589-592

S. Bernardini, J.M. Portal, P. Masson, J.M. Gallière, M. Renovell, Impact of gate reduction failure on analog application: example of the current mirror, LATW , Cartagena (Colombie), ISBN 958-33-5900-9, 2004, p. 12-17

S. Bernardini, J.M. Portal, P. Masson, A tunneling model for gate oxide failure in deep sub-micron technology, DATE’2004 , Vol. 2, ISBN 0-7695-2085-5, 2004, p. 1404-1406

L. Lopez, D. Née, P. Masson, R. Bouchakour, A low cost test vehicule for embedded DRAM capacitor investigation and monitoring of the process, IRPS, 2004, p. 498-501

R. Ranica, A. Villaret, P. Malinge, P. Mazoyer, D. Lenoble, P. Candelier, F. Jacquet, P. Masson, R. Bouchakour, R. Fournel, J.P. Schoellkopf, T. Skotnicki; A One Transistor Cell on Bulk Substrate (1T-Bulk) for Low-Cost and High Density eDRAM, VLSI Technology Symposium, Hawai(USA), 2004, p. 128-129

R. Ranica, A. Villaret, P. Mazoyer, S. Monfray, D.Chanemougame, P. Masson, C. Dray, P. Waltz, R. Bez, T. Skotnicki, A new SONos structure based on backside trapping for nanoscale memory applications, VLSI Silicon Nanoworkshop, 2004

X. Cuinet, S. Bernardini, P. Masson, L. Raymond, Simulation of nanometric roughness on a MOS capacitance, 5 nd French-Italian Symposium on SiO 2 and advanced dielectrics, juin 2004

L. Perniola, S. Bernardini, G. Iannaccone, B. De Salvo, G. Ghibaudo, P. Masson, C. Gerardi, Channel Hot Electron Impact on Electrical Characteristics of Discrete-Trap Memories, ESSDERC 2004 , Leuven (Belgium), 2004, p. 249-252

R . Ranica, A. Villaret, C. Fenouillet-Beranger, P. Malinge, P. Mazoyer, P. Masson, D. Delille, C. Charbuillet, P. Candelier, T. Skotnicki, A capacitor-less DRAM cell on very thin film and 75nm gate length Fully Depleted device for high density embedded memories, IEDM, 2004, p. 277-280

R. Ranica, A. Villaret, P. Malinge, G. Gasiot, P. Mazoyer, P. Roche, P. Candelier, F. Jacquet, P. Masson, R. Bouchakour, R. Fournel, J.P. Schoellkopf, T. Skotnicki, Scaled 1T-Bulk devices built with CMOS 90 nm technology for low-cost eDRAM applications, VLSI Technology Symposium , Kyoto (Japon), ISBN: 4-900784-00-1, 2005, p. 38-39

L. Lopez, P. Masson, D. Nee, R. Bouchakour, A model to explain the C-V curves of DRAM capacitors with silicon electrodes and trapping dielectrics, ICMTD’05, Giens (France), 2005, p. 85-88

K.Castellani-Coulié, D. Munteanu, J.L. Autran, V. Ferlet-Cavrois, P. Paillet, P. Masson, Device simulation study of SEU in SRAMs based on double-gate MOSFETs, ICMTD’05, Giens (France), 2005, p. 93-96

R. Ranica, A. Villaret, P. Malinge, P. Candelier, P. Masson, R. Bouchakour, P. Mazoyer, T. Skotnicki, 1T-Bulk DRAM cell with improved performances: the way to scaling, ICMTD 2005 , p. 59-52

G. Bossu, C. Charbuillet, R. Ranica, A. Villaret, D. Chanemougame, S. Monfray, S. Borel, F. Leverd, P. Masson, P. Mazoyer, : A quasi non volatile low power memory cell, VLSI Silicon Nanoworkshop , 2006

S. Puget, G. Bossu, A. Regnier, R. Ranica, A. Villaret, P. Masson, G. Ghibaudo, P. Mazoyer, T. Skotnicki, Quantum effects influence on thin silicon film capacitor-less DRAM performance, International SOI conference, N ew York (USA), ISBN: 1-4244-0290-5 , 2006, p. 157-158

A. Régnier, B. Saillet, J.M. Portal, B. Delsuc, R. Laffont, P. Masson, R. Bouchakour, MM11 Based Flash Memory Cell Model Including Characterization Procedure, Proceedings of the IEEE International Symposium on Circuits and Systems, Ile de Kos ( Grèce), ISBN: 0-7803-9389-9 , 2006, p. 3518-3521

A. Regnier, J.M. Portal, H. Aziza, P. Masson, R. Bouchakour, C. Relliaud, D. Née, J.M. Mirabel, EEPROM Compact Model with SILC Simulation Capability, IEEE Non Volatile Memory Technology Symposium, San Mateo (USA), ISBN: 0-7803-9738-X , 2006, p. 26-30

R. Wacquez, R. Cerutti, P. Coronel, A. Cros, D. Fleury, A. Pouydebasque, J. Bustos, S. Harrison, N. Loubet, S. Borel, D. Lenoble, D. Delille, F. Leverd, F. Judong, M.P. Samson, N. Vuillet, B. Guillaumot, T. Ernst, P. Masson, T. Skotnicki, A Novel Self Aligned Design Adapted Gate All Around (SADAGAA) MOSFET including two stacked Channels: A High Co-Integration Potential, SSDM, 2006

S. Puget, G. Bossu, C. Guerin, R. Ranica, A.Villaret, P. Masson, J-M. Portal, R. Bouchakour, P. Mazoyer, V. Huard, T. Skotnicki, 1TBulk eDRAM a reliable concept for nanometre scale high density and low power applications, 2 nd International Conference on Memory Technology and Design (ICMTD’07), may 7-10, Giens (France), 2007

S. Puget, G. Bossu, P. Mazoyer, J.M. Portal, P. Masson, R. Bouchakour, Thomas Skotnicki, On the Potentiality of Planar Independent Double Gate for Capacitorless eDRAM, IEEE Silicon Nanoelectronics Workshop (SNW), june 15-16, Honolulu (USA), 2008

G. Bossu, S. Puget, P. Masson, J-M. Portal, R. Bouchakour, P. Mazoyer, T. Skotnicki, Independent Double Gate - Potential for Non-Volatile Memories, IEEE Silicon Nanoelectronics Workshop (SNW), june 15-16, Honolulu (USA), 2008

G. Bossu, A. Demolliens, S. Puget, P. Masson, J.M. Portal, R. Bouchakour, P. Mazoyer, T. Skotnicki, A new embedded NVM thin film cell for low voltage applications, International conference on Solid State Devices and Materials (SSDM), September 23-26, Ibaraki (Japan) 2008

S. Puget, G. Bossu, F. Berthollet, P. Mazoyer, J.M. Portal, P. Masson, R. Bouchakour, T. Skotnicki, 1TBulk eDRAM Using Gate-Induced Drain-Leakage (GIDL) Current for High Speed and Low Power applications, International conference on Solid State Devices and Materials (SSDM), September 23-26, Ibaraki (Japan), 2008

S. Puget, G. Bossu, P. Mazoyer, J.M. Portal, P. Masson, R. Bouchakour, Thomas Skotnicki, On the Potentiality of Planar Independent Double Gate for Capacitorless eDRAM, IEEE Silicon Nanoelectronics Workshop (SNW), June 15-16, Honolulu (USA), 2008, p. poster 2-27

G. Bossu, S. Puget, P. Masson, J-M. Portal, R. Bouchakour, P. Mazoyer, T. Skotnicki, Independent Double Gate - Potential for Non-Volatile Memories, IEEE Silicon Nanoelectronics Workshop (SNW), June 15-16, Honolulu (USA), 2008, p. poster 2-23

S. Puget, G. Bossu, C. Fenouillet-Beranger, P. Perreau, P. Masson, P. Lorenzini, P. Mazoyer, J-M. Portal, R. Bouchakour, T. Skotnicki, FDSOI Floating Body Cell eDRAM Using Gate-Induced Drain-Leakage (GIDL) Write Current for High Speed and Low Power Applications, International Memory Workshop, Monterey (USA), may 2009

S. Puget, J-M. Portal, P. Masson, P. Mazoyer, G. Bossu, P. Lorenzini, R. Bouchakour, T. Skotnicki, Optimization of Independent Double Gate Floating Body Cell DRAM Performance by Technology Screening, Silicon Nano-Workshop, Kyoto (Japan), june 13-14 2009

S. Puget, G. Bossu, P. Masson, P. Mazoyer, J-M. Portal, P. Lorenzini, D. Rideau, R. Bouchakour, T. Skotnicki , Quantum Effect Modeling in Thin Film Independent Double Gate Capacitorless eDRAM, ESSDERC 2009, 14-18 September - Athens- Greece, 2009

Y. Joly, L. Lopez, J.-M. Portal, H. Aziza, P. Masson, J.-L. Ogier, Y. Bert, F. Julien, P. Fornara. Octagonal MOSFET: Reliable Device for Low Power Analog Applications, ESSDERC 2011, 12-16 September 2011

R. Llido, P. Masson, A. Regnier, V. Goubier, G. Haller, V. Pouget, D. Lewis, Effects of 1064 nm laser on MOS capacitor, October ESREF 2012,

P. Chiquet, P. Masson, R. Laffont, G. Micolau, J. Postel-Pellerin, F. Lalande, B. Bouteille, J-L. Ogier, Investigation of the effects of constant voltage stress on thin SiO 2 layers using dynamic measurement protocols, October ESREF 2012

P. Chiquet, P. Masson, G. Micolau, R. Laffont, J. Postel-Pellerin, F. Lalande, B. Bouteille, A. Regnier, A new fast gate current measurement protocol for the study of transient regimes in metal-oxide-semiconductor structures, Symposium “SiO 2, Advanced Dielectrics and Related Devices” June 2012

G. Just, J.-L. Ogier, A. Regnier, J. Postel-Pellerin, F. Lalande, P.Masson, Impact of Poly-Reoxidation Process Step on Tunnel Oxide Reliability: Charge Trapping and Data Retention, Symposium “SiO 2, Advanced Dielectrics and Related Devices” June 2012,

G. Just, V. Della Marca, A. Regnier, J.-L. Ogier, J. Postel-Pellerin, F. Lalande, J.-M Portal, P. Masson, Effects of Lightly Doped Drain and Channel Doping Variations on Flash Memory Performances and Reliability, VARI, 11-12 June 2012, p. (INVITED)

P. Chiquet, P. Masson, G. Micolau, R. Laffont, F. Lalande, J. Postel-Pellerin, A. Regnier, Determination of physical properties of semiconductor-oxide-semiconductor structures using a new fast gate current measurement protocol, IEEE ICSD Bologna 2013

B. Rebuffat, V. Della Marca, J-L. Ogier, P. Masson, Effect of Ions Presence in the SiOCH Inter Metal Dielectric Structure, ESSDERC 2013

B. Rebuffat, P. Masson, J-L. Ogier M. Mantelli, R. Laffont, Effect of AC Stress on Oxide TDDB and Trapped Charge in Interface States, International Symposium on Integrated Circuits (ISIC), December 10-12, 2014

J. Innocenti, L. Welter, F. Julien, J.-M. Portal, L. Lopez, J. Sonzogni, P. Masson, S. Niel, A. Regnier, “Dynamic power reduction through process and design optimizations on CMOS 80 nm embedded non-volatile memories technology,” IEEE 57th Int. Midwest Symp. Circuits Syst., pp. 897–900, 2014.

J. Innocenti, F. Julien, J. M. Portal, L. Lopez, Q. Hubert, P. Masson, J. Sonzogni, S. Niel, A. Regnier, “Layout Optimizations to Decrease Internal Power and Area in Digital CMOS ” 38th Int. Conv. Inf. Commun. Technol. Electron. Microelectron., 2015.

J. Innocenti, C. Rivero, F. Julien, J. M. Portal, Q. Hubert, G. Bouton, P. Fornara, L. Lopez, P. Masson, “NMOS Drive Current Enhancement by Reducing Mechanical Stress Induced by Shallow Trench Isolation,” IEEE 11th Int. Conf. Electron Devices Solid-State Circuits, pp. 395–398, 2015.

B. Rebuffat, J-L. Ogier, M. Mantelli, P. Masson and R. Laffont, “Relaxation Effect on Cycling on NOR Flash Memories “, IEEE Conference On Electron Devices and Solid-State Circuits (EDSSC), Hong Kong, Juin 2015 , 2015

J. Innocenti, L. Welter, N. Borrel, F. Julien, J. M. Portal, J. Sonzogni, L. Lopez, P. Masson, S. Niel, “Dynamic Current Reduction of CMOS Digital Circuits through Design and Process Optimization,” 25th Int. Work. on Power Timing Model. Optim. Simul. (PATMOS), In proc, 2015.

P. Chiquet, J. Postel-Pellerin, C. Tuninetti, S. Souiki, P. Masson, "Effect Of Short Pulsed Program/Erase Cycling On Flash Memory Devices", 14th IMEKO TC10 Workshop on Technical Diagnostics New Perspectives in Measurements, Tools and Techniques for systems reliability, maintainability and safety, Milan, Italy, June 27-28, 2016

T. Kempf, M. Mantelli, F. Maugain, A. Regnier, J.-M. Portal, P. Masson, J.-M. Moragues, M. Hesse, V. Della Marca, F. Julien & S. Niel, “Impact of CMOS post nitridation annealing on reliability of 40nm 512kB embedded Flash array”, International Integrated Reliability Workshop, Fallen Leaf Lake, USA, 20176

D. Morillon, C. Pribat, F. Julien, N. Cherault, J. Goy, O. Gourhant, J.-L. Ogier, P. Masson, G. Ghezzi, T. Kempf, J. Delalleau, A. Villaret, J.-C. Grenier & S. Niel, “Study of HTO-based alternative gate oxides for high voltage transistors on advanced eNVM technology”, International Integrated Reliability Workshop, Fallen Leaf Lake, USA, 2017

D. Morillon, F. Julien, J. Coignus, A. Toffoli, L. Welter, C. Jahan, J.-P. Reynard, E. Richard & P. Masson, “High voltage MOSFETs integration on advanced CMOS technology: Characterization of thick gate oxides incorporating high k metal gate stack from logic core process”, IEEE ICMTS, Grenoble, France, 2017

T. Kempf, V. Della Marca, L. Baron, F. Maugain, F. La Rosa, S. Niel, A. Regnier, J.-M. Portal, P. Masson, Threshold voltage bitmap analysis methodology: Application to a 512kB 40nm Flash memory test chip, IEEE International Reliability Physics Symposium (IRPS), Burlingame, CA, USA, 2018

T. Kempf, V. Della Marca, P. Canet, A. Regnier, P. Masson, J.-M. Portal, A new method for chip test and single 40nm NOR Flash cell electrical parameters correlation using a cast structure, International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA), Hsinchu, Taiwan, 2018 (DOI: 10.1109/VLSI-TSA.2018.8403859)

D. Morillon, P. Masson, F. Julien, P. Lorenzini, J. Goy, C. Pribat, O. Gourhant, T. Kempf, J-L Ogier, A Villaret, G Ghezzi, N Cherault and S Niel, Gate Oxide Degradation Assessment by Electrical Stress and Capacitance Measurements, International Integrated Reliability Workshop, Stanford Sierra Conference Center, CA, USA, 2018

P. Devoge, H. Aziza, P. Lorenzini, P. Masson, F. Julien, A. Marzaki, A. Malherbe, J. Delalleau, T. Cabout, A. Regnier, S. Niel, Hot-carrier reliability and performance study of a variable gate-to-drain/source overlap transistor, ESREF (European Symposium on Reliability of Electron Devices Failure Physics and Analysis), Berlin, 2022

P. Devoge, H. Aziza, P. Lorenzini, P. Masson, F. Julien, A. Marzaki, A. Malherbe, J. Delalleau, T. Cabout, A. Regnier, S. Niel, Gate-to-drain/source overlap and asymmetry effects on hot-carrier generation, accept IIRW (IEEE International Integrated Reliability Workshop) 2022

P. Devoge, H. Aziza, P. Lorenzini, P. Masson, F. Julien, A. Marzaki, A. Malherbe, J. Delalleau, T. Cabout, A. Regnier, S. Niel, Schmitt trigger to benchmark the performance of a new zero-cost transistor, IECS, 2022